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Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
POWER MANAGEMENT Description
The SC1470 is a single output, constant on-time synchronous-buck PWM controller intended for use in notebook computers and other battery operated portable devices. Features include high efficiency and fast dynamic response with no minimum on time. The excellent transient response means that SC1470 based solutions will require less output capacitance than competing fixed frequency converters. The frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady state operation. At light loads, Power-Save Mode enables the SC1470 to skip PWM pulses for better efficiency. The output voltage can be adjusted from 0.5V to VCCA. A frequency setting resistor sets the on-time for flexibility in choosing filter components. The integrated gate drivers feature adaptive shoot-through protection and soft switching. Additional features include cycle-by-cycle current limit, digital soft-start, over-voltage and undervoltage protection, and a Power Good output.
SC1470
Features
Constant on-time for fast dynamic response Programmable VOUT range = 0.5 - VCCA VBAT range = 1.8V - 25V DC current sense using low-side RDS(ON) sensing or sense resistor Resistor programmable frequency Cycle-by-Cycle current limit Digital soft-start Combined EN and PSAVE functions Over-voltage/under-voltage fault protection and Power Good output 10A typical shutdown current Low quiescent power dissipation 14 Lead TSSOP package Industrial temperature range 1% Internal reference (2% system DC accuracy) Integrated gate drivers with soft switching
Applications
Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies
Typical Application Circuit
VBAT 5VSUS
5VSUS
VBAT
D1 R1 RTON R2 10R 1 2 VOUT R3 R5 3 4 5 6 R6 7 U1 EN/PSV TON VOUT VCCA FB PGD VSSA SC1470 BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 C4 1uF R4 L1 VOUT C3 + Q2 C1 0.1uF Q1 C2 10uF
PGOOD
C5 1nF
C6 1uF
Revision: April 29, 2005
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SC1470
POWER MANAGEMENT Absolute Maximum Ratings (1)
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter TON to VSSA DH, BST to PGND LX to PGND PGND to VSSA BST to LX DL, ILIM, VDDP to PGND EN/PSV, FB, PGD, VCCA, VOUT to VSSA VCCA to EN/PSV, FB, PGD, VOUT Thermal Resistance Junction to Ambient (2) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +0.3 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0
Units V V V V V V V V C/W C C C
JA TJ TSTG TLEAD
100 -40 to +125 -65 to +150 300
Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
Electrical Characteristics
Test Conditions: VBAT = 15V, EN/PSV = 5V, VCCA = VDDP = 5V, VOUT = 1.25V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Input Supplies VC C A VD D P VBAT Input Voltage VDDP Operating Current VCCA Operating Current TON Operating Current Shutdown Current Offtime > 800ns FB > regulation point, ILOAD = 0A FB > regulation point, ILOAD = 0A RTON = 1M EN/PSV = 0V VC C A VDDP, TON 1.8 70 700 15 -5 5 0 -10 10 1 5.0 5.0 25 150 1100 4.5 4.5 5.5 5.5 V V V A A A A A A
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SC1470
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV = 5V, VCCA = VDDP = 5V, VOUT = 1.25V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Controller Error Comparator Threshold (FB Turn-on Threshold)(1) Output Voltage Range On-Time, VBAT = 2.5V RTON = 1M RTON = 500k Minimum Off Time VOUT Input Resistance FB Input Bias Current Over-Current Sensing ILIM Sink Current Current Comparator Offset PSAVE Zero-Crossing Threshold Fault Protection Current Limit (Positive) (2) (PGND-LX), RILIM = 5k (PGND-LX), RILIM = 10k (PGND-LX), RILIM = 20k Current Limit (Negative) Output Under-Voltage Fault Output Over-Voltage Fault Over-Voltage Fault Delay PGD Low Output Voltage PGD Leakage Current PGD UV Threshold (PGND-LX) With respect to internal reference With respect to internal reference FB forced above OV threshold Sink 1mA FB in regulation, PGD = 5V With respect to internal reference -10 -12 50 100 200 -140 -30 +10 5 0.4 1 -8 35 85 175 -200 -40 +8 65 115 225 -100 -25 +12 mV mV mV mV % % s V A % (PGND - LX), EN/PSV = 5V 5 mV DL High PGND - ILIM 10 9 -5 11 5 A mV 1761 936 400 500 -1.0 +1.0 VCCA = 4.5V to 5.5V 0.500 -1% 0.5 1497 796 +1% VC C A 2025 1076 550 V V ns ns ns k A
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SC1470
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV = 5V, VCCA = VDDP = 5V, VOUT = 1.25V, RTON = 1M
Parameter
Conditions Min
25C Typ 5 4.0 165 Max
-40C to 125C Min Max
Units
PGD Fault Delay VCCA Undervoltage Threshold Over Temperature Lockout Inputs/Outputs Logic Input Low Voltage Logic Input High Voltage Logic Input High Voltage EN/PSV Input Resistance
FB forced outside PGD window. Falling (100mV Hysteresis) 10C Hysteresis
s 3.7 4.3 V C
EN/PSV low EN High, PSV low (Floating) EN/PSV high R Pullup to VCCA R Pulldown to VSSA 1.5 1.0 2.0 3.1
1.2
V V V M M
Soft Start Soft-Start Ramp Time Under-Voltage Blank Time Gate Drivers Shoot-Through Delay (4) DL Pull-Down Resistance DL Pull-Up Resistance DH Pull-Down Resistance DH Pull-Up Resistance DL Sink Current DL Source Current DH Sink/Source Current
(5)
EN/PSV high to PGD high EN/PSV high to UV high
440 440
clks(3) clks(3)
DH or DL rising DL low DL high DH low, BST - LX = 5V DH high, BST - LX = 5V DL = 2.5V DL = 2.5V DH = 2.5V
30 0.8 2 2 2 3.1 1.3 1.3 1.6 4 4 4
ns A A A
Notes: (1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the lowside MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests. (3) clks = switching cycles. (4) Guaranteed by design. See Shoot-Through Delay Timing Diagram. (5) Semtech's SmartDriverTM FET drive first pulls DH high with a pullup resistance of 10 (typ.) until LX = 1.5V (typ.). At this point, an additional pullup device is activated, reducing the resistance to 2 (typ.). This negates the need for an external gate or boost resistor.
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SC1470
POWER MANAGEMENT Pin Configuration Ordering Information
DEVICE
(1)
Top View
EN/PSV TON VOUT VCCA FB PGD VSSA 1 2 3 4 5 6 7 14 13 12 11 10 9 8 BST DH LX ILIM VDDP DL PGND
PACKAGE TSSOP-14 TSSOP-14 EVALUATION BOARD
SC1470ITSTR SC1470ITSTRT(2) S C 1470E V B
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free option. This product is fully WEEE and RoHS compliant.
(14 Pin TSSOP)
Pin Descriptions
Pin # 1 Pin Name EN/PSV Pin Function Enable/Power Save input. Pull down to VSSA to shut down the output. Pull up to enable the output and activate PSAVE mode. Float to enable the output and activate continuous conduction mode (CCM). If floated, bypass to VSSA with a 10nF ceramic capacitor. This pin is used to sense VBAT through a pullup resistor, RTON, and to set the top MOSFET ontime. Bypass this pin with a 1nF ceramic capacitor to VSSA. Output voltage sense input. Connect to the output at the load. Supply voltage input for the analog supply. Use a 10 Ohm / 1F RC filter from 5VSUS to VSSA. Feedback input. Connect to a resistor divider located at the IC from VOUT to VSSA to set the output voltage from 0.5V to VCCA. Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles) following power up. Ground reference for analog circuitry. Connect to PGND at the bottom of the output capacitor. Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Decouple this pin with a 1F ceramic capacitor to PGND. Current limit input. Connect to drain of low-side MOSFET for RDS(ON) sensing or the source for resistor sensing through a threshold sensing resistor. Phase node (junction of top and bottom MOSFETs and the output inductor) connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive.
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2 3 4 5 6 7 8 9 10 11 12 13 14
TON VOUT VC C A FB PGD VSSA PGND DL VD D P ILIM LX DH BST
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SC1470
POWER MANAGEMENT Shoot-Through Delay Timing Diagram
LX
DH
DL DL tplhDL tplhDH
Block Diagram
VCCA (4) EN/SPV (1)
POR / SS
OT
BST (14) TON (2) VOUT (3) TON ON OFF PWM TOFF CONTROL LOGIC HI DH (13) LX (12)
OC 1.5V REF + FB (5) X3 LO PGD (6) OV VSSA (7) FAULT MONITOR UV REF + 10% REF - 10% REF - 30% ZERO I ISENSE ILIM (11) VDDP (10) DL (9) PGND (8)
Figure 1 - SC1470 Block Diagram
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SC1470
POWER MANAGEMENT Application Information
+5V Bias Supplies The SC1470 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951. For optimal operation, the controller has its own ground reference, VSSA, which should be tied by a single trace to PGND at the negative terminal of the output capacitor (see Layout Guidelines). All external components referenced to VSSA in the Typical Applications Circuit on Page 1 should be connected to VSSA. The supply decoupling capacitor should be tied directly between the VCCA and VSSA pins. A 10 resistor should be used to decouple VCCA from the main VDDP supply. PGND can then be a separate plane which is not used for routing traces. All PGND connections are connected directly to the ground plane with special attention given to avoiding indirect connections which may create ground loops. As mentioned above, VSSA must be connected to the PGND plane at the negative terminal of the output capacitor only. The VDDP input provides power to the upper and lower gate drivers. A decoupling capacitor is required. No series resistor between VDDP and 5V is required. See Layout Guidelines for more details. Pseudo-fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant ontime, pseudo fixed frequency PWM controller (see Figure 1, SC1470 Block Diagram). The output ripple voltage developed across the output filter capacitor's ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns. On-Time One-Shot (tON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage-proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from
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zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need for a clock generator. For VOUT < 3.3V:
V t ON = 3.3 x10 -12 * (R TON + 37 x10 3 ) * OUT + 50ns V BAT For 3.3V VOUT 5V: V t ON = 0.85 * 3.3 x10 -12 * (R TON + 37x103 ) * OUT + 50ns V BAT RTON is a resistor connected from the input supply (VBAT) to the TON pin. Due to the high impedance of this resistor, the TON pin should always be bypassed to VSSA using a 1nF ceramic capacitor.
Enable & Psave The EN/PSV pin enables the supply. When EN/PSV is tied to VCCA the controller is enabled and power save will also be enabled. If PSAVE is enabled, the SC1470 PSAVE comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (LX) to PGND. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve light-load efficiency and add hysteresis, the on-time is increased by 50% in power save. The efficiency improvement at light-loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when psave is enabled. When the EN/PSV pin is tri-stated, an internal pull-up will activate the controller and power save will be disabled. When the EN/PSV pin is pulled low, the supply is disabled and the MOSFET drivers are tri-stated.
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SC1470
POWER MANAGEMENT
Output Voltage Selection The output voltage is set by the feedback resistors R3 & R7 of Figure 2 below. The internal reference is 1.5V, so the voltage at the feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can be set to a minimum of 0.5V. The equation for setting the output voltage is: sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. In an extreme overcurrent situation, the top MOSFET will never turn back on and eventually the part will latch off due to output undervoltage (see Output Undervoltage Protection). The current sensing circuit actually regulates the inductor valley current (see Figure 3). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below:
R3 VOUT = 1 + * 0 .5 R7
1 2 VOUT C5 56p 0402 R3 20k0 0402 3 4 5 6 R7 14k3 0402 7
U1 EN/PSV TON VOUT VCCA FB PGD VSSA
SC1470 BST DH LX ILIM VDDP DL PGND
14 13 12 11 10 9 8
INDUCTOR CURRENT
IPEAK ILOAD ILIMIT
TIME Valley Current-Limit Threshold Point
Figure 2: Setting The Output Voltage Current Limit Circuit Current limiting of the SC1470 can be accomplished in two ways. The on-state resistance of the low-side MOSFET can be used as the current sensing element or sense resistors in series with the low-side source can be used if greater accuracy is desired. RDS(ON) sensing is more efficient and less expensive. In both cases, the RILIM resistor between the ILIM pin and LX pin sets the over current threshold. This resistor RILIM is connected to a 10A current source within the SC1470 which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resistor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the
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Figure 3: Valley Current Limiting The equation for the current limit threshold is as follows:
ILIMIT = 10e -6 *
RILIM A R SENSE
Where (referring to Figure 4 on Page 15) RILIM is R4 and RSENSE is the RDS(ON) of Q2. For resistor sensing, a sense resistor is placed between the source of Q2 and PGND. The current through the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches the voltage drop across RILIM, a positive over-current exists and the high side MOSFET will not be allowed to turn on. When using an external sense resistor RSENSE is the resistance of the sense resistor.
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SC1470
POWER MANAGEMENT
The current limit circuitry also protects against negative over-current (i.e. when the current is flowing from the load to PGND through the inductor and bottom MOSFET). In this case, when the bottom MOSFET is turned on, the phase node, LX, will be higher than PGND initially. The SC1470 monitors the voltage at LX, and if it is greater than a set threshold voltage of 125mV (nom.) the bottom MOSFET is turned off. The device then waits for approximately 2.5s and then DL goes high for 300ns (typ.) once more to sense the current. This repeats until either the over-current condition goes away or the part latches off due to output overvoltage (see Output Overvoltage Protection). Power Good Output The power good output is an open-drain output and requires a pull-up resistor. When the output voltage is 10% above or below its set voltage, PGD gets pulled low. It is held low until the output voltage returns to within +/-10% of the output set voltage. PGD is also held low during start-up and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. There is a 5s delay built into the PGD circuitry to prevent false transitions. Output Overvoltage Protection When the output exceeds 10% of the its set voltage the low-side MOSFET is latched on. It stays latched on and the controller is latched off until reset (see below). There is a 5s delay built into the OV protection circuit to prevent false transitions. Output Undervoltage Protection When the output is 30% below its set voltage the output is latched in a tri-stated condition. It stays latched and the controller is latched off until reset (see below). There is a 5s delay built into the UV protection circuit to prevent false transitions. Note: to reset from any fault, VCCA or EN/PSV must be toggled. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA exceeds 3V, starting up the internal biasing. VCCA undervoltage lockout (UVLO) circuitry inhibits the controller until VCCA rises above 4.2V. At this time the UVLO circuitry resets the fault latch and soft-start counter,
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and allows switching to occur if the device is enabled. Switching always starts with DL to charge up the BST capacitor. With the softstart circuit (automatically) enabled, it will progressively limit the output current (by limiting the current out of the ILIM pin) over a predetermined time period of 440 switching cycles. The ramp occurs in four steps: 1) 110 cycles at 25% ILIM with double minimum off-time (for purposes of the on-time one-shot, there is an internal positive offset of 120mV to VOUT during this period to aid in startup) 2) 110 cycles at 50% ILIM with normal minimum off-time 3) 110 cycles at 75% ILIM with normal minimum off-time 4) 110 cycles at 100% ILIM with normal minimum off-time. At this point the output undervoltage and power good circuitry is enabled. There is 100mV of hysteresis built into the UVLO circuit and when VCCA falls to 4.1V (nom.) the output drivers are shut down and tristated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off (below ~1V). Semtech's SmartDriverTM FET drive first pulls DH high with a pullup resistance of 10 (typ.) until LX = 1.5V (typ.). At this point, an additional pullup device is activated, reducing the resistance to 2 (typ.). This negates the need for an external gate or boost resistor. The adaptive dead time circuit also monitors the phase node, LX, to determine the state of the high side MOSFET, and prevents the low side MOSFET from turning on until DH is fully off (LX below ~1V). Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 550ns (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times.
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SC1470
POWER MANAGEMENT
The IC duty-factor limitation is given by:
DUTY =
t ON( MIN ) t ON( MIN )
schematic in Figure 4 on Page 15 will be designed. The maximum input voltage (VBAT(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (VBAT(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a VBAT range of 8V to 20V. Four parameters are needed for the output: 1) nominal output voltage, VOUT (we will use 1.2V) 2) static (or DC) tolerance, TOLST (we will use +/-4%) 3) transient tolerance, TOLTR and size of transient (we will use +/-8% and 6A for purposes of this demonstration). 4) maximum output current, IOUT (we will design for 6A) Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. A default RtON value of 1M is suggested as a starting point, but this is not set in stone. The first thing to do is to calculate the on-time, tON, at VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT, VOUT and RtON. For VOUT < 3.3V:
VOUT -9 t ON _ VBAT(MIN) = 3.3 * 10 -12 * (R tON + 37 * 103 ) * + 50 * 10 s VBAT (MIN)
+ t OFF(MAX )
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC1470 System DC Accuracy Two IC parameters affect system DC accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. The error comparator threshold does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. The on pulse in the SC1470 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be VOUT. For example: if VOUT is 2.5V and the ripple is 50mV with VBAT = 6V, then the measured DC output will be 2.525V. If the ripple increases to 80mV with VBAT = 25V, then the measured DC output will be 2.540V. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. It will not change the frequency. Switching frequency variation with load can be minimized by choosing MOSFETs with lower R DS(ON). High R DS(ON) MOSFETs will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. Design Procedure Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. For purposes of demonstrating the procedure the output for the
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and
VOUT -9 t ON _ VBAT (MAX ) = 3.3 * 10 -12 * (R tON + 37 * 10 3 ) * + 50 * 10 s VBAT (MAX )
From these values of tON we can calculate the nominal switching frequency as follows:
fSW _ VBAT (MIN ) =
and
VOUT (VBAT (MIN) * t ON _ VBAT (MIN) )Hz
fSW _ VBAT (MAX ) =
VOUT (VBAT(MAX ) * t ON _ VBAT(MAX ) )Hz
tON is generated by a one-shot comparator that samples
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SC1470
POWER MANAGEMENT
VBAT via RtON, converting this to a current. This current is used to charge an internal 3.3pF capacitor to VOUT. The equations above reflect this along with any internal components or delays that influence tON. For our example we select RtON = 1M: tON_VBAT(MIN) = 563ns and tON_VBAT(MAX) = 255ns fSW_VBAT(MIN) = 266kHz and fSW_VBAT(MAX) = 235kHz Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of IOUT which will give us a starting place. For our example: IINDUCTOR(MIN) = 7.1A(MIN) Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (R ESR_ST(MAX)) and transient ESR (R ESR_TR(MAX)):
RESR _ ST (MAX ) =
(ERR
ST
- ERRDC ) * 2
IRIPPLE _ VBAT (MAX )
Ohms
L VBAT (MIN) = (VBAT (MIN) - VOUT ) *
and
t ON _ VBAT (MIN)
OUT
(0.5 * I )
H
Where ERRST is the static output tolerance and ERRDC is the DC error. The DC error will be 1% plus the tolerance of the feedback resistors, thus 2% total for 1% feedback resistors. For our example:
L VBAT (MAX ) = (VBAT (MAX ) - VOUT ) *
For our example:
t ON _ VBAT (MAX )
(0.5 * I )
OUT
H
ERRST = 48mV and ERRDC = 24mV, therefore RESR_ST(MAX) = 22m
LVBAT(MIN) = 1.3H and LVBAT(MAX) = 1.6H We will select an inductor value of 2.2H to reduce the ripple current, which can be calculated as follows:
RESR _ TR (MAX ) =
(ERR
TR
- ERR DC )
I IOUT + RIPPLE _ VBAT (MAX ) 2
Ohms
IRIPPLE _ VBAT (MIN) = (VBAT (MIN) - VOUT ) *
and
t ON _ VBAT (MIN) L
A P -P
Where ERRTR is the transient output tolerance. Note that this calculation assumes that the worst case load transient is full load. For half of full load, divide the IOUT term by 2. For our example: ERRTR = 96mV and ERRDC = 24mV, therefore
IRIPPLE _ VBAT (MAX ) = (VBAT (MAX ) - VOUT ) *
t ON _ VBAT (MAX ) L
A P -P
For our example: IRIPPLE_VBAT(MIN) = 1.74AP-P and IRIPPLE_VBAT(MAX) = 2.18AP-P From this we can calculate the minimum inductor current rating for normal operation:
RESR_TR(MAX) = 10.2m for a full 6A load transient We will select a value of 12.5m maximum for our design, which would be achieved by using two 25m output capacitors in parallel. Note that for constant-on converters there is a minimum ESR requirement for stability which can be calculated as follows:
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IINDUCTOR (MIN) = IOUT (MAX ) +
IRIPPLE _ VBAT (MAX ) 2
A (MIN)
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SC1470
POWER MANAGEMENT
RESR (MIN ) 3 = 2 * * COUT * fSW
value of VFB based upon the selected CTOP:
R BOT = VRIPPLE _ VBAT(MIN) * 1 RBOT + 1 + 2 * * fSW _ VBAT(MIN) * C TOP R TOP VP -P
This criteria should be checked once the output capacitance has been determined. Now that we know the output ESR we can calculate the output ripple voltage:
VFB _ VBAT(MIN)
For our example: VFB_VBAT(MIN) = 14.8mVP-P - good Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, VOUT_ST_POS, when a load release occurs:
VRIPPLE _ VBAT(MAX) = RESR * IRIPPLE _ VBAT(MAX) VP -P
and
VRIPPLE _ VBAT(MIN) = RESR * IRIPPLE _ VBAT(MIN) VP -P
For our example: VRIPPLE_VBAT(MAX) = 27mVP-P and VRIPPLE_VBAT(MIN) = 22mVP-P Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mVP-P at minimum V BAT , and worst case no smaller than 10mV P-P . If VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component values should be revisited in order to improve this. Quite often a small capacitor, CTOP, is required in parallel with the top feedback resistor, RTOP, in order to ensure that V FB is large enough. C TOP should not be greater than 100pF. The value of CTOP can be calculated as follows, where R BOT is the bottom feedback resistor. Firstly calculating the value of ZTOP required:
VOUT _ ST _ POS = VOUT + ERRDC V
For our example: VOUT_ST_POS = 1.224V
POSLIM TR = VOUT * TOL TR V
Where TOLTR is the transient tolerance. For our example: POSLIMTR = 1.296V The minimum output capacitance is calculated as follows:
I IOUT + RIPPLE _ VBAT (MAX ) 2 =L* F 2 2 POSLIM TR - VOUT _ ST _ POS
2
Z TOP
R = BOT * (VRIPPLE _ VBAT (MIN) - 0.015 )Ohms 0.015
C OUT (MIN)
Secondly calculating the value of CTOP required to achieve this:
1 1 - Z TOP R TOP F = 2 * * fSW _ VBAT (MIN)
(
)
C TOP
This calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps my be calculated by substituting the desired current for the IOUT term. For our example: COUT(MIN) = 610F. We will select 440F, using two 220F, 25m capacitors in parallel. For smaller load release overshoot,
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For our example we will use R TOP = 20.0k and RBOT = 14.3k, therefore: ZTOP = 6.67k and CTOP = 60pF We will select a value of CTOP = 56pF. Calculating the
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POWER MANAGEMENT
660F may be used. Alternatively, one 15m or 12m 220F, 330F or 470F capacitor may be used (with the appropriate change to the calculation for C TOP), depending upon the load transient requirements. Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage: Where: TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows:
IIN(RMS ) = VOUT * (VBAT (MIN) - VOUT ) *
For our example: IIN(RMS) = 2.14ARMS
IOUT VBAT _ MIN
A RMS
PD = VCCA * IVCCA + VDDP * IVDDP + Vg * Q g * f + VBST * 1mA * D W
Input capacitors should be selected with sufficient ripple current rating for this RMS current, for example a 10F, 1210 size, 25V ceramic capacitor can handle approximately 3A RMS . Refer to manufacturer's data sheets. Finally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the "valley current", which is the average output current minus half the ripple current. We use the maximum room temperature specification for MOSFET RDS(ON) at VGS = 4.5V for purposes of this calculation:
Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) VDDP = gate drive supply voltage (V) IVDDP = gate drive operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) VBST = boost pin voltage during tON (V) D = duty cycle Inserting the following values for VBAT(MIN) condition (since this is the worst case condition for power dissipation in the controller) as an example (VOUT = 1.2V): TA = 85C JA = 100C/W VCCA = VDDP = 5V IVCCA = 1100A (data sheet maximum) IVDDP = 150A (data sheet maximum) Vg = 5V Qg = 60nC f = 266kHz VBAT(MIN) = 8V VBST(MIN) = VBAT(MIN)+VDDP = 13V D(MIN) = 1.2/8 = 0.15 gives us:
IVALLEY = IOUT -
IRIPPLE _ VBAT (MIN) 2
A
The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions.
RILIM = (IVALLEY * 1.2) *
For our example:
RDS( ON) * 1.4 10 * 10 - 6
Ohms
IVALLEY = 5.13A, RDS(ON) = 9m and RILIM = 7.76k We select the next lowest 1% resistor value: 7.68k Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA
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PD = 5 * 1100 * 10 -6 + 5 * 150 * 10 -6 + 5 * 60 * 10 -9 * 266 * 10 3 + 13 * 1 * 10 -3 * 0.15 = 0.088 W
and:
TJ = 85 + 0.088 * 100 = 93 .8 C
C
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As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout.
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SC1470
POWER MANAGEMENT
Layout Guidelines
VBAT 5VSUS 5VSUS VBAT
R1 1M 0402
R2 10R 0402
1 2
U1 EN/PSV TON VOUT VCCA FB PGD VSSA
SC1470 BST DH LX ILIM VDDP DL PGND
14 13 12 11 10 9 C9 8
D1 SOD323 C1 0.1uF 0603
Q1 IRF7811AV
C2 2n2/50V 0402 L1 2u2
C3 0u1/25V 0603
C4 10u/25V 1210
VOUT C5 56p 0402 R3 20k0 0402
3 4 5 6
R4 7k87 0402 Q2 FDS6676S R6 0R (1) 0402 C6 + 220u/25m 7343 + C7
VOUT
220u/25m 7343
PGOOD R7 14k3 0402
C8 1nF 0402
C10 1uF 0603
7
1uF 0603
N OTES (1) R 6 is not required but aids k eeping VSSA s eparate f rom PGN D ex c ept where des ired in lay out.
VBAT = 8V to 20V VOUT = 1.2V @ 6A Figure 4: Reference Design One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground reference, VSSA, should be kept separate from power ground. All components that are referenced to VSSA should connect to it locally at the chip. VSSA should connect to power ground at the output capacitor(s) only. The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the feedback trace with VSSA as a differential pair from the output capacitor back to the chip. Run them in a "quiet layer" if possible. VSSA may be separated from PGND using a zero Ohm resistor (that will be placed at the bottom of the output capacitors) to aid in net separation. Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins (VDDP and PGND, VCCA and VSSA) and connected directly to them on the same side. Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use "minimum" land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in more detail.
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SC1470
POWER MANAGEMENT
The layout can be considered in two parts, the control section referenced to VSSA and the power section. Looking at the control section first, locate all components referenced to VSSA on the schematic and place these components at the chip. Connect VSSA using either a wide (>0.020") trace or a copper pour if room allows. Very little current flows in the chip ground therefore large areas of copper are not needed.
VBAT 5VSUS 5VSUS
R1 1M 0402
R2 10R 0402
1 2
U1 EN/PSV TON VOUT VCCA FB PGD VSSA
SC1470 BST DH LX ILIM VDDP DL PGND
14 13 12 11 10 9 C9 8
VOUT C5 56p 0402 R3 20k0 0402
3 4 5 6
PGOOD R7 14k3 0402
C8 1nF 0402
C10 1uF 0603
7
1uF 0603
Figure 5: Components Connected to VSSA
Figure 6: Example VSSA 0.020" Trace In Figure 6 above, all components referenced to VSSA have been placed and have been connected using a 0.020" trace. Decoupling capacitors C9 and C10 are as close as possible to their pins. C9 should connect to the ground plane using two vias.
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POWER MANAGEMENT
As shown below, VOUT and VSSA should be routed as a differential pair to the output capacitor(s).
U2 EN/PSV TON VOUT VCCA FB PGD VSSA SC470 BST DH LX ILIM VDDP DL PGND
1 2 VOUT C6 56p 0402 R4 20k0 0402 3 4 5 6 R8 14k3 0402 7 C11 1uF 0603
14 13 12 11 + 10 R12 0R (2) 9 8 0402 220u/25m 7343 220u/25m 7343 VOUT C14 + C7
VSSA VOUT
Figure 7: Differential Routing of Feedback and Ground Reference Traces Next, the schematic in Figure 8 below shows the power section. The highest di/dts occur in the input loop (highlighted in red) and thus this loop should be kept as small as possible.
VBAT
Q1 IRF7811AV
C2 2n2/50V 0402 L1 2u2
C3 0u1/25V 0603
C4 10u/25V 1210
VOUT C6 + Q2 FDS6676S R6 0R (2) 220u/25m 7343 + 220u/25m 7343 C7
0402
Figure 8: Power Section and Input Loop The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. See Figure 9 for an example.
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POWER MANAGEMENT
Figure 9: Power Component Placement and Copper Pours Key points for the power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. 4) Notice in Figure 9 above placement of the 0 resistor at the bottom of the output capacitor to connect to VSSA. 5) The current limit resistor should be placed as close as possible to the ILIM and LX pins. Connecting the control and power sections should be accomplished as follows (see Figure 10 below): 1) Route VSSA and VOUT as a differential pair routed in a "quiet" layer away from noise sources. 2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. 3) BST is also a noisy node and should be kept as short as possible. 4) Connect PGND pin on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the ground plane.
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1 2 3 4 5 6 7 U1 EN/PSV TON VOUT VCCA FB PGD VSSA SC470 BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 R4 0402 7k87 Q1 IRF7811AV
L1
2u2
Q2 FDS6676S
Figure 10: Connecting the Control and Power Sections
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SC1470
POWER MANAGEMENT Typical Characteristics
1.2V Efficiency (Power Save Mode) vs. Output Current vs. Input Voltage
100 95 90 85 Efficiency (%) 80 75 70 65 60 55 50 0 1 2 3 IOUT (A) 4 5 6 Efficiency (%) VBAT = 20V VBAT = 8V 100 95 90 85 80 75 70 65 60 55 50 0 1 2 3 IOUT (A) 4 5 6 VBAT = 20V VBAT = 8V
1.2V Efficiency (Continuous Conduction Mode) vs. Output Current vs. Input Voltage
1.2V Output Voltage (Power Save Mode) vs. Output Current vs. Input Voltage
1.220 1.216 1.212 1.208 VOUT (V) 1.204 1.200 1.196 1.192 1.188 1.184 1.180 0 1 2 3 IOUT (A) 4 5 6 VBAT = 8V VBAT = 20V
1.2V Output Voltage (Continuous Conduction Mode) vs. Output Current vs. Input Voltage
1.220 1.216 1.212 1.208 VOUT (V) 1.204 1.200 1.196 1.192 1.188 1.184 1.180 0 1 2 3 IOUT (A) 4 5 6 VBAT = 8V VBAT = 20V
1.2V Switching Frequency (Power Save Mode) vs. Output Current vs. Input Voltage
400 VBAT = 8V 350 300 Frequency (kHz) 250 200 150 100 50 0 0 1 2 3 IOUT (A) 4 5 6
1.2V Switching Frequency (Continuous Conduction Mode) vs. Output Current vs. Input Voltage
400 VBAT = 8V 350 300 Frequency (kHz)
VBAT = 20V
250 200 150 100 50 0 0 1 2
VBAT = 20V
3 IOUT (A)
4
5
6
Please refer to Figure 4 on Page 15 for test schematic
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SC1470
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Transient Response, Continuous Conduction Mode, 0A to 6A to 0A Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40s/div.
Load Transient Response, Continuous Conduction Mode, 0A to 6A Zoomed Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Load Transient Response, Continuous Conduction Mode, 6A to 0A Zoomed Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Please refer to Figure 4 on Page 15 for test schematic
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SC1470
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Transient Response, Power Save Mode, 0A to 6A to 0A Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40s/div.
Load Transient Response, Power Save Mode, 0A to 6A Zoomed Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Load Transient Response, Power Save Mode, 6A to 0A Zoomed Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Please refer to Figure 4 on Page 15 for test schematic
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SC1470
POWER MANAGEMENT Typical Characteristics (Cont.)
Startup (PSV), EN/PSV Going High Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div.
Startup (CCM), EN/PSV 0V to Floating Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div.
Please refer to Figure 4 on Page 15 for test schematic
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SC1470
POWER MANAGEMENT Marking Information Top Mark Bottom Mark
yy = two-digit year of manufacture ww = two-digit week of manufacture
xxxxxx = Wafer Lot Number xx = Assembly Lot Number
Outline Drawing - TSSOP-14
A D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX
.047 .006 .002 .042 .031 .012 .007 .003 .007 .193 .197 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 14 0 8 .004 .004 .008 1.20 0.15 0.05 1.05 0.80 0.19 0.30 0.20 0.09 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 14 0 8 0.10 0.10 0.20
2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 B E
e
aaa C SEATING PLANE
D A2 A H GAGE PLANE 0.25 (L1) DETAIL SIDE VIEW SEE DETAIL L c
C bxN bbb
A1 C A-B D
01
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB-1.
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SC1470
POWER MANAGEMENT Land Pattern - TSSOP-14
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2005 Semtech Corp. 25 www.semtech.com

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